FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 8

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note 1:
Note 2:
Note 3:
PIN NO.
111:118
100
102
103
104
105
106
107
108
109
110
119
120
94
96
97
98
99
nCS -This pin is the active low chip select, it must be low for all chip accesses. For 12 bit
addressing, SA0:SA11, this input should be tied to GND. For 16 bit address qualification,
address bits SA12:SA15 can be "ORed" together and applied to this pin. If IDE2 is not
used, SA12 can be connected to nCS, pin 27 to SA13, pin 28 to SA14 and pin 29 to SA15.
nYY - The "n" as the first letter of a signal name indicates an "Active Low" signal.
nHDCS2 and nHDCS3 require a pull-up to ensure a logic high at power-up when used for
IDE2 until the Active Bit is set to 1.
Mouse Clock
GP I/O; IRQ in
GP I/O; IRQ in
GP I/O; WD Timer Output /IRRX
GP I/O; Power Led output /IRTX
GP I/O; GP Address Decode
GP I/O; GP Write Strobe
GP I/O; JOY Read Strobe/JOYCS
GP I/O; Joy Write Strobe
GP I/O; IDE2 Output Enable/8042 P20
GP I/O; Serial EEPROM Data In
GP I/O; Serial EEPROM Data Out
GP I/O; Serial EEPROM Clock
GP I/O; Serial EEPROM Enable
GP I/O; 8042 P21
ROM Bus (I/O to the SD Bus)
ROM Chip Select (only used for ROM)
ROM Output Enable (DIR) (only used for ROM)
NAME
DESCRIPTION OF PIN FUNCTIONS
GENERAL PURPOSE I/O
BIOS BUFFERS
8
MCLK
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
RD[0:7]
nROMCS
nROMDIR
SYMBOL
BUFFER TYPE
I/OD16P
I/O24
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I/O4
I
I