FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 144

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Chip Level
Vendor Defined
TEST 1
TEST 2
TEST 3
Default = 0x00, on
POR or Reset_Drv
hardware signal.
REGISTER
0x25 -0x2C Reserved - Writes are ignored, reads return 0.
ADDRESS
0x2E R/W
0x2E R/W
0x2F R/W
Table 62 - Chip Level Registers
= 0 IRQ8 is active high
= 1 IRQ8 is active low
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
Test Modes: Reserved for SMSC. Users should not
write to this register, may produce undesired
results.
144
DESCRIPTION
STATE
C
C
C