FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 11

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

SUPER I/O REGISTERS
The address map, shown below in Table 1,
shows the addresses of the different blocks of
the Super I/O immediately after power up. The
base addresses of the FDC, IDE, serial and
parallel
configuration registers.
used to access more than one register.
Note 1:
Base+(0-5) and +(7)
Base+(0-7)
Base+(0-7)
Base+(0-3)
Base+(0-7)
Base+(0-3), +(400-402)
Base+(0-7), +(400-402)
Base1+(0-7), Base2+(0)
Base1+(0-7), Base2+(0)
ports
Refer to the configuration register descriptions for setting the base address
can
ADDRESS
be
Some addresses are
moved
Table 1 - Super I/O Block Addresses
FUNCTIONAL DESCRIPTION
via
Floppy Disk
Serial Port Com 1
Serial Port Com 2
Parallel Port
SPP
EPP
ECP
ECP+EPP+SPP
IDE 1
IDE 2
BLOCK NAME
the
11
HOST PROCESSOR INTERFACE
The host processor communicates with the
FDC37C93x through a series of read/write
registers. The port addresses for these registers
are shown in Table 1.
accomplished through programmed I/O or DMA
transfers. All registers are 8 bits wide except
the IDE data register at port 1F0H which is 16
bits wide. All host interface output buffers are
capable of sinking a minimum of 12 mA.
LOGICAL
DEVICE
0
4
5
3
1
2
IR Support
NOTES
Register access is