FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 107

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The FDC37C93x contains two IDE interfaces.
This
controllers (AT or IDE) to be interfaced to the
host processor. The IDE interface performs the
address
generates the buffer enables for external buffers
and provides internal buffers for the low byte
IDE data transfers. For more information, refer
to the IDE pin descriptions and the ATA
specification. The following example uses IDE1
base1=1F0H,
base1=170H, base2 =376H.
HOST FILE REGISTERS
The Host File Registers are accessed by the AT
Host.
TASK FILE REGISTERS
Task File Registers may be accessed by the
host AT when pin nHDCS0 is active (low). The
Data Register (1F0H) is 16 bits wide; the
remaining task file registers are 8 bits wide. The
task file registers are ATA and EATA
enables hard disks with embedded
There are two groups of registers,
FIGURE 2 - HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE)
decoding
base2=3F6H
PRIMARY
1F0H
1F7H
3F6H
INTEGRATED DRIVE ELECTRONICS INTERFACE
for
the
IDE
and
SECONDARY
interface,
170H
177H
376H
IDE2
107
the AT Task File, and the Miscellaneous AT
Register.
ADDRESS 1F0H-1F7H; 170H-177H
These AT registers contain the Task File
Registers. These registers communicate data,
command, and status information with the AT
host, and are addressed when nHCS0 or nHCS2
is low.
ADDRESS 3F6H/376H;
These AT registers may be used by the BIOS for
drive control.
interface when nHCS1 or nHCS3 is active low.
Figure 2 shows the AT Host Register Map.
compatible. Please refer to the ATA and EATA
specifications. These are available from:
TASK FILE REGISTERS
MISC. AT REGISTERS
Global Engineering
2805 McGaw Street
Irvine, CA 92714
[phone] or
[phone]
They are accessed by the AT