FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 5

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FDC37C935-QS

Manufacturer Part Number
FDC37C935-QS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of FDC37C935-QS

Lead Free Status / RoHS Status
Supplier Unconfirmed
101, 125,
123, 130
PIN NO.
1, 8, 40,
21, 60,
71, 95,
67:61,
82,84,
81,83,
72:79
41:52
59:54
86,88
85,87
139
53
70
90
80
89
68
69
35
36
22
37
38
39
17
12
11
System Data Bus
System Address Bus
Chip Select/SA12 (Active Low)(Note 1)
Address Enable (DMA master has bus control)
I/O Channel Ready
Reset Drive
Interrupt Requests [1,3:12,14,15]
(Polarity control for IRQ8)
DMA Requests
DMA Acknowledge
Terminal Count
I/O Read
I/O Write
Serial Clock Out (24 MHz)
16 MHz Out
14.318MHz Clock Input
14.318MHz Clock Output 1
14.318MHz Clock Output 2
14.318MHz Clock Output 3
+5V Supply Voltage
Ground
Read Disk Data
Write Gate
Write Disk Data
PROCESSOR/HOST INTERFACE
NAME
DESCRIPTION OF PIN FUNCTIONS
FDD INTERFACE
POWER PINS
5
SD[0:7]
SA[0:11]
nCS
AEN
IOCHRDY
RESET_DRV
IRQ[1,3:12,
14,15]
DRQ[0:3]
nDACK[0:3]
TC
nIOR
nIOW
24CLK
16CLK
CLOCKI
CLKO1
CLKO2
CLKO3
VCC
GND
nRDATA
nWGATE
nWDATA
SYMBOL
BUFFER TYPE
O16SR
OD24
OD24
OD48
OD48
I/O24
08SR
08SR
08SR
08SR
ICLK
O24
IS
IS
I
I
I
I
I
I
I

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