FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 128

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

RTC INTERRUPT
The interrupt generated by the RTC is an active
high output. The RTC interrupt output remains
high as long as the
interrupt is present and the corresponding
interrupt-enable
RESET_DRV or reading register C clears the
RTC interrupt.
The
programming
All 14 bytes are directly writable and readable by
the host with the following exceptions:
a.
Registers C and D are read only
ADDRESS
RTC
E-FF
A
B
C
D
0
1
2
3
4
5
6
7
8
9
Interrupt
the
bit
RTC
is
REGISTER TYPE
status bit causing the
is
set.
Table 56 - Real Time Clock Address Map
Primary
brought out by
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Activating
Interrupt
Register 0: Seconds
Register 1: Seconds Alarm
Register 2: Minutes
Register 3: Minutes Alarm
Register 4: Hours
Register 5: Hours Alarm
Register 6: Day of Week
Register 7: Date of Month
Register 8: Month
Register 9: Year
Register A:
Register B: (Bit 0 is Read Only)
Register C:
Register D:
Register E-FF: General purpose
128
Select to a non-zero value. If IRQ 8 is selected
then
programmable through a bit in the OSC Global
Configuration Register.
INTERNAL REGISTERS
Table 56 shows the address map of the RTC,
ten bytes of time, calendar, and alarm data, four
control and status bytes, 241 bytes of "CMOS"
registers and one RTC control register.
b.
c.
d.
Bit 7 of Register A is read only
Bits 0 of Register B is read only
Bits 7-1 of the Shared RTC Control register
are read only.
REGISTER FUNCTION
the polarity of this IRQ 8 output is