FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 27

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Model 30 Mode
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 Kbps after a
hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in
the CCR register.
RESET
COND.
See Table 11 for the settings
CHG
DSK
N/A
7
6
0
0
5
0
0
27
4
0
0
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in
the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the pin.
DMAEN NOPREC DRATE
3
0
2
0
SEL1
1
1
DRATE
SEL0
0
0