FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 66

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

The FDC37C93x incorporates two full function
UARTs.
NS16450, the 16450 ACE registers and the
NS16550A.
parallel conversion on received characters and
parallel-to-serial
characters. The data rates are independently
programmable from 460.8K baud down to 50
baud. The character options are programmable
for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky
or no parity; and prioritized interrupts. The
UARTs each contain a programmable baud rate
generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535.
The UARTs are also capable of supporting the
MIDI data rate. Refer to the Configuration
Registers for information on disabling, power
They
DLAB*
The UARTS perform serial-to-
0
0
0
X
X
X
X
X
X
X
1
1
conversion
are
compatible
*NOTE: DLAB is Bit 7 of the Line Control Register
A2
0
0
0
0
0
0
1
1
1
1
0
0
Table 31 - Addressing the Serial Port
on
A1
0
0
0
1
1
1
0
0
1
1
0
0
SERIAL PORT (UART)
with
transmit
A0
0
0
1
0
0
1
0
1
0
1
0
1
the
66
Receive Buffer (read)
Transmit Buffer (write)
Interrupt Enable (read/write)
Interrupt Identification (read)
FIFO Control (write)
Line Control (read/write)
Modem Control (read/write)
Line Status (read/write)
Modem Status (read/write)
Scratchpad (read/write)
Divisor LSB (read/write)
Divisor MSB (read/write
down and changing the base address of the
UARTs. The interrupt from a UART is enabled
by programming OUT2 of that UART to a logic
"1".
UART's interrupt.
supports IrDA, HP-SIR and ASK-IR infrared
modes of operation.
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below.
addresses of the serial ports are defined by the
configuration
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37C93x contains two
serial ports, each of which contain a register set
as described below.
REGISTER NAME
OUT2 being a logic "0" disables that
registers
The second UART also
(see
Configuration
The base