FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 179

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FDC37C935-QS

Manufacturer Part Number
FDC37C935-QS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of FDC37C935-QS

Lead Free Status / RoHS Status
Supplier Unconfirmed
Note 1: The nRESET low time is dependent upon the processor clock. The nRESET must be active
NAME
NAME
t1
t2
t1
t2
X 1 K
t4
R E S E T
for a minimum of 24 x16MHz clock cycles.
Clock Cycle Time for 14.318MHZ
Clock High Time/Low Time for 14.318MHz
Clock Cycle Time for 32KHZ
Clock High Time/Low Time for 32KHz
Clock Rise Time/Fall Time (not shown)
nRESET Low Time (Note 1)
FIGURE 7A - INPUT CLOCK TIMING
DESCRIPTION
DESCRIPTION
FIGURE 7B - RESET TIMING
t1
179
t4
t2
MIN
25
MIN
1.5
t2
TYP
TYP
MAX
MAX
65
5
UNITS
UNITS
ns
ns
ns
s

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