FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 21

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset.
data
Configuration Control Register (CCR) not the
DSR,
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a
software reset, and are set to 250 Kbps after a
hardware reset.
BIT 2 through 4
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal.
precompensation values for the combination of
these bits settings.
starting track number to start precompensation.
the configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into manual low power mode. The
floppy controller
circuits will be turned off.
this starting track number can be changed by
rate
for
RESET
COND.
PC/AT
See Table 11 for the settings
is
RESET
S/W
programmed
clock
7
0
and
Track 0 is the default
PRECOMPENSATION
Table 10 shows the
POWER
DOWN
and data separator
PS/2
The controller will
6
0
using
Model
5
0
0
The
the
30
COMP2
PRE-
21
4
0
applications can set the data rate in the DSR.
The data rate of the floppy controller is the most
recent write of either the DSR or CCR. The DSR
is unaffected by a software reset. A hardware
reset
corresponds to the default precompensation
setting and 250 Kbps.
come out of manual low power mode after a
software reset or access to the Data Register or
Main Status Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is
self clearing.
COMP1
PRE-
Table 10 - Precompensation Delays
PRECOMP
3
0
will
432
111
001
010
011
100
101
110
000
set
COMP0
PRE-
2
0
the
PRECOMPENSATION
Default: See Table 12
<2Mbps
DSR
Default
125.00
166.67
208.33
250.00
DRATE
41.67
83.34
0.00
SEL1
DELAY (nsec)
1
1
to
DRATE
SEL0
02H,
0
0
Default
2Mbps
104.2
20.8
41.7
62.5
83.3
125
0
which