FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 134

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

REGISTER C (CH) - READ ONLY REGISTER
IRQF
The interrupt request flag is set to a "1" when
one or more of the following are true:
Any time the IRQF bit is a "1", the IRQB signal
is driven low. All flag bits are cleared after
Register C is read or by the RESET_DRV port.
PF
The periodic interrupt flag is a read only bit
which is set to a "1" when a particular edge is
detected on the selected tap of the divider chain.
The RS3 -RS0 bits establish the periodic rate.
PF is set to a "1" independent of the state of
the PIE bit. PF being a "1" sets the IRQF bit
and initiates an IRQB signal when PIE is also a
"1". The PF bit is cleared by RESET_DRV or by
a read of Register C.
IRQF
MSB
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
b7
PF
b6
AF
b5
UF
b4
134
AF
The alarm interrupt flag when set to a "1"
indicates that the current time has matched the
alarm time. A "1" in AF causes a "1" to appear in
IRQF and the IRQB port to go low when the AIE
bit is also a "1". A RESET_DRV or a read of
Register C clears the AF bit.
UF
The update-ended interrupt flag bit is set after
each update cycle. When the UIE bit is also a
"1", the "1" in UF causes the IRQF bit to be set
and asserts IRQB. A RESET_DRV or a read of
Register C causes UF to be cleared.
b3-0
The unused bits of Register C are read as zeros
and cannot be written.
b3
0
b2
0
b1
0
LSB
b0
0