FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 121

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Write EEPROM Data Register, 0xF3
Bits[7:0]
This register allows the host to write data into
the serial EEPROM. The FDC37C93x supports
serial EEPROMS with x16 configurations. Two
bytes must be written to this register in order to
generate a EEPROM write cycle.
leads the MSB. The first write to this register
resets bit 0 of the Write Status register. The
second write resets bit 1 of the Write Status
register and generates a write cycle to the serial
EEPROM. The Write Status register must be
polled before performing a pair of writes to this
register.
Write Status Register, 0xF4
Bits[1:0]
When = (1,1)Indicates that the Write EEPROM
Data register is ready to accept a pair of bytes.
When = (1,0) bit 0 is cleared on the first write of
the Write EEPROM Data register. This status
indicates that the serial device controller has
received one byte (LSB) and is waiting for the
second byte (MSB).
When = (0,0) bit 1 is cleared on the second
write of the Write EEPROM Data register
indicating that two bytes have been accepted
and that the serial device interface is busy
writing the word to the EEPROM.
Bits[6:2]
Reserved, set to zero
Bit[7]
This bit is cleared to configure the EEPROM
interface for Read operations. Clearing this bit
enables the serial EEPROM prefetch when the
Serial EEPROM Pointer Register is updated
(written or auto-incremented).
The LSB
121
interface for Write operations. Setting this bit
disables the serial EEPROM prefetch when the
Serial EEPROM Pointer Register is updated
(written or auto-incremented).
Read EEPROM Data Register, 0xF5
Bits[7:0]
This register allows the host to read data from
the serial EEPROM. Data is not valid in this
register until bit 0 of the Read Status Register is
set. Since the EEPROM is a 16-bit device this
register presents the LSB followed by the MSB
for each pair of register reads. Immediately after
the MSB is read bit-0 of the Read Status
Register will be cleared, then the Serial
EEPROM
incremented, then the next word of EEPROM
data will be fetched, followed by the Read
Status Register, bit 0 being set.
Read Status Register, 0xF6
Bit[0]
When set, indicates that data in the Read
EEPROM Data register is valid.
cleared when EEPROM Data is read until the
next byte is valid. Reading the Read EEPROM
Data register when bit 0 is clear will have no
detremental effects;
invalid.
GATEA20
GATEA20 is an internal signal from the
Keyboard controller (Port 21). The FDC37C93x
may be configured to drive this signal onto
GP25 by programming its GPI/O Configuration
Register.
Pointer
Register
the data will simply be
will
This bit is
be
auto-