FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 149

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
Note:
Note:
Note:
Interrupt
request level
select 0
DMA Channel
select 0
NAME
NAME
An Interrupt is activated by setting the Interrupt Request Level Select 0 register to a non-zero
value AND :
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
for the PP logical device by setting IRQE, bit D4 of the Control Port and in addition
for the PP logical device in ECP mode by clearing serviceIntr, bit D2 of the ecr.
for the Serial Port logical device by setting any combination of bits D0-D3 in the IER and by
setting the OUT2 bit in the UART's Modem Control (MCR) Register.
for the RTC by (refer to the RTC section of this spec.)
for the KYBD by (refer to the KYBD controller section of this spec.)
IRQ pins must tri-state if not used/selected by any Logical Device. Refer to Appendix A
A DMA channel is activated by setting the DMA Channel Select 0 register to [0x00-0x03] AND
:
for the FDC logical device by setting DMAEN, bit D3 of the Digital Output Register.
for the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr.
DMAREQ pins must tri-state if not used/selected by any Logical Device. Refer to Appendix A
0x70 (R/W)
Table 66 - DMA Channel Select Configuration Register Description
REG INDEX
0x74 (R/W)
Table 65 - Interrupt Select Configuration Register Description
REG INDEX
Bits[3:0] selects which interrupt level is used for Interrupt 0.
Note: All interrupts are edge high (except ECP/EPP)
0x00=no interrupt selected.
0x01=IRQ1
0x02=IRQ2
0x0E=IRQ14
0x0F=IRQ15
Bits[2:0] select the DMA Channel.
o
o
o
0x00=DMA0
0x01=DMA1
0x02=DMA2
0x03=DMA3
0x04-0x07= No DMA active
149
DEFINITION
DEFINITION
STATE
STATE
C
C