FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 164

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Note:
WDT_CTRL
Default = 0x00
NAME
This register is also available at index 03 when not in configuration mode. See Table 47B.
Table 74 - Auxilliary I/O, Logical Device 8 [Logical Device Number = 0x08]
REG INDEX
0xF4
Watch-dog timer Control
Bit[0] Watch-dog Status Bit, R/W
=1
=0 WD timer counting
Bit[1] Power LED Toggle Enable, R/W
=1 Toggle Power LED at 1Hz rate with 50 percent
=0 Disable Power LED Toggle
Bit[2] Force Timeout, W
=1 Forces WD timeout event; this bit is self-clearing
Bit[3] P20 Force Timeout Enable, R/W
= 1 Allows rising edge of P20, from the Keyboard
= 0 P20 activity does not generate the WD timeout
Note: The P20 signal will remain high for a minimum
of 1us and can remain high indefinitely. Therefore,
when P20 forced timeouts are enabled, a self-
clearing edge-detect circuit is used to generate a
signal which is ORed with the signal generated by
the Force Timeout Bit.
Bits[7:4] Reserved - Set to 0
duty cycle. (1/2 sec. on, 1/2 sec. off)
WD timeout occured
Controller, to force the WD timeout event. A
WD timeout event may still be forced by
setting the Force Timeout Bit, bit 2.
event.
164
DEFINITION
STATE
C