FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 89

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

EXTENDED CAPABILITIES PARALLEL PORT
ECP provides a number of advantages, some of
which are listed below. The individual features
are explained in greater detail in the remainder
of this section.
Vocabulary
The following terms are used in this document:
assert
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DRQ selected by the Configuration Registers.
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
High performance half-duplex forward and
reverse channel
Interlocked handshake, for fast reliable
transfer
Optional single byte RLE compression for
improved throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
When a signal asserts it transitions to a
"true" state, when a signal deasserts it
transitions to a "false" state.
Addr/RLE
compress
nBusy
PD7
D7
0
0
intrValue
MODE
nAck
PD6
D6
0
0
Direction
PError
PD5
D5
0
Parallel Port IRQ
Parallel Port Data FIFO
nErrIntrEn
ECP Data FIFO
ackIntEn
Select
PD4
Test FIFO
D4
1
Address or RLE field
89
reverse Peripheral to Host communication.
PWord A port word; equal in size to the width
1
0
These terms may be considered synonymous:
Reference Document
IEEE 1284 Extended Capabilities Port Protocol
and ISA Interface Standard, Rev 1.09, Jan 7,
1993.
Microsoft.
The bit map of the Extended Parallel Port
registers is:
SelectIn
dmaEn
nFault
PeriphClk, nAck
HostAck, nAutoFd
PeriphAck, Busy
nPeriphRequest, nFault
nReverseRequest, nInit
nAckReverse, PError
Xflag, Select
ECPMode, nSelectln
HostClk, nStrobe
PD3
D3
0
of
implementation, PWord is always 8
bits.
A high level.
A low level.
This document is available from
serviceIntr
the
PD2
nInit
D2
0
0
Parallel Port DMA
ISA
autofd
interface.
PD1
full
D1
0
0
strobe
empty
PD0
D0
0
0
For
Note
2
1
1
2
2
2
this