FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 125

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

may be required.
KEYBOARD POWER MANAGEMENT
The keyboard provides support for two power-
saving modes: soft powerdown mode and hard
powerdown mode.
the clock to the ALU is stopped but the
timer/counter and interrupts are still active. In
hard power down mode the clock to the 8042 is
stopped.
power wherever possible!
Soft Power Down Mode
This mode is entered by executing a HALT
instruction. The execution of program code is
halted until either RESET is driven active or a
data byte is written to the DBBIN register by a
master CPU. If this mode is exited using the
interrupt, and the IBF interrupt is enabled, then
program execution resumes with a CALL to the
interrupt routine, otherwise the next instruction
is executed. If it is exited using RESET then a
normal reset sequence is initiated and program
execution starts from program memory location
0.
Hard Power Down Mode
This mode is entered by executing a STOP
instruction.
disabling
UD
D7
the
Efforts must be made to reduce
The oscillator is stopped by
UD
D6
oscillator driver cell.
In soft powerdown mode,
UD
D5
Table 54 - Status Register
When
UD
D4
125
written to the DBBIN register by a master
CPU, this mode will be exited (as above).
However, as the oscillator cell will require an
initialization time, either RESET must be held
active for sufficient time to allow the oscillator to
stabilise.
above.
INTERRUPTS
The
interrupts. IBF and the Timer/Counter Overflow.
MEMORY CONFIGURATIONS
The FDC37C93x provides 2K of on-chip ROM
and 256 bytes of on-chip RAM.
Register Definitions
Host I/F Data Register
The Input Data register and Output Data register
are each 8 bits wide. A write to this 8 bit register
will load the Keyboard Data Read Buffer, set the
OBF flag and set the KIRQ output if enabled. A
read of this register will read the data from the
Keyboard Data or Command Write Buffer and
clear the IBF flag. Refer to the KIRQ and Status
register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide.
shows the contents of the Status register.
C/D
D3
FDC37C93x
Program execution will resume as
UD
D2
provides
IBF
D1
the
two
Table 54
OBF
D0
8042