FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 136

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

FREQUENCY DIVIDER
The RTC has 22 binary divider stages following
the clock input. The output of the divider is a 1
Hz signal to the update-cycle logic. The divider
is controlled by the three divider bits (DV3-DV0)
control bits can select the operating mode, or
be used to hold the divider chain reset which
allows precision setting of the time. When the
divider chain is changed from reset to the
operating mode, the first update cycle is
one-half second later. The divider control bits
are also used to facilitate testing of the RTC.
PERIODIC INTERRUPT SELECTION
The periodic interrupt allows the IRQB port to be
triggered from once every 500 ms to once every
122.07 us. As Table 60 shows, the periodic
interrupt is selected with the RS0-RS3 bits in
Register A. The periodic interrupt is enabled
with the PIE bit in Register B.
POWER MANAGEMENT
The RAMD signal controls all bus input to the
RTC and RAM (nIOW, nIOR, RESET_DRV).
When asserted, it disallows any modification of
the RTC and RAM data by the host or 8051.
RAMD is asserted whenever:
V
When the V
voltage, the RTC switches to battery power.
in Register A. As shown in Table 59 the divider
CC
Hyster=1 implies that VCC <4.0 volts +/-0.25V; Hyster=0 implies that VCC >4.0 volts +/-0.25V.
is below 4.0 volts nominal.
CC
VCC
<4.0
>4.0
voltage drops below the battery
HYSTER
1
0
BATTERY
136
1
x
RTC switches back to system power. When the
V
inputs are locked out so that the internal
registers cannot be modified by the system. This
lockout condition continues for 62 msec (min) to
125 msec (max) after the system power has
been restored.
occur under the following conditions:
1.
2.
3.
To minimize power consumption, the oscillator
is not operational under the following conditions:
4.
5.
If the battery voltage is between 1 volt nominal
and 2.4 volt nominal when V
6.
CC
The Divider Chain Controls (bits 6-4) are in
any mode but Normal Operation ("010").
The VRT bit is a "0".
When battery voltage is below 1 volt
nominal and RESET_DRV is a "1".
will also initialize all registers 00-0D to a
"00".
The Divider Chain Controls (bits 6-4) are in
Oscillator Disabled mode (000, or 001).
If V
and then re-applied (a new battery is
installed) the following occurs:
a.
b.
Clear VRT bit to "0". Maintain all other RTC
bits in the state as before V
voltage drops below 4.0 volts nominal, all
CC
CC
The oscillator is disabled immediately.
Initialize all registers 00-0D to a "00"
when V
=0 and the battery power is removed
REGISTER ACCESS
CC
The 62 msec lockout does not
is applied.
N
Y
CC
is applied:
CC
was applied
This