MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 117
MC9S12XDP512CAL
Manufacturer Part Number
MC9S12XDP512CAL
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDP512CAL.pdf
(1348 pages)
Specifications of MC9S12XDP512CAL
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
91
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
2(16-chx10-bit)
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
112
Package Type
LQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
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2.6.2
The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed, either from
a locked state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the
LOCKIE bit to 0. The PLL Lock interrupt flag (LOCKIF) is set to1 when the LOCK condition has
changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
2.6.3
The CRG generates a self clock mode interrupt when the SCM condition of the system has changed, either
entered or exited self clock mode. SCM conditions can only change if the self clock mode enable bit
(SCME) is set to 1. SCM conditions are caused by a failing clock quality check after power on reset (POR)
or low voltage reset (LVR) or recovery from full stop mode (PSTP = 0) or clock monitor failure. For details
on the clock quality check refer to
enabled (CME = 1) a loss of external clock will also cause a SCM condition (SCME = 1).
SCM interrupts are locally disabled by setting the SCMIE bit to 0. The SCM interrupt flag (SCMIF) is set
to1 when the SCM condition has changed, and is cleared to 0 by writing a 1 to the SCMIF bit.
Freescale Semiconductor
PLL Lock Interrupt
Self Clock Mode Interrupt
Section 2.4.1.4, “Clock Quality
MC9S12XDP512 Data Sheet, Rev. 2.21
Chapter 2 Clocks and Reset Generator (S12CRGV6)
Checker”. If the clock monitor is
117
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