MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 879

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.4
Each pin except PE0, PE1, and BKGD can act as general purpose I/O. In addition each pin can act as an
output from the external bus interface module or a peripheral module or an input to the external bus
interface module or a peripheral module.
A set of configuration registers is common to all ports with exceptions in the expanded bus interface and
ATD ports
not become active.
This device does not become active while the port is used as a push-pull output.
1
22.4.1
22.4.1.1
This register holds the value driven out to the pin if the pin is used as a general purpose I/O.
Writing to this register has only an effect on the pin if the pin is used as general purpose output. When
reading this address, the buffered state of the pin is returned if the associated data direction register bit is
set to “0”.
If the data direction register bits are set to logic level “1”, the contents of the data register is returned. This
is independent of any other configuration
Freescale Semiconductor
Port
AD0
AD1
Each cell represents one register with individual configuration bits
M
A
B
C
D
E
K
S
P
H
T
J
Example: Selecting a pull-up device
Functional Description
Data
(Table
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Registers
Data Register
22-67). All registers can be written at any time; however a specific configuration might
Direction
Data
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
Table 22-67. Register Availability per Port
Input
yes
yes
yes
yes
yes
yes
—
—
—
—
—
—
—
—
MC9S12XDP512 Data Sheet, Rev. 2.21
Reduced
(Figure
Drive
yes
yes
yes
yes
yes
yes
yes
yes
yes
22-76).
Enable
Pull
yes
yes
yes
yes
yes
yes
yes
yes
yes
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
Polarity
Select
yes
yes
yes
yes
yes
—
—
—
—
—
—
—
—
—
1
Wired-OR
Mode
yes
yes
—
—
—
—
—
—
—
—
—
—
—
—
Interrupt
Enable
yes
yes
yes
—
—
—
—
—
—
—
—
—
—
—
Interrupt
Flag
yes
yes
yes
—
—
—
—
—
—
—
—
—
—
—
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