MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 454

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
10.3.3.3
This register keeps the data length field of the CAN frame.
454
Module Base + 0x0004 (DSR0)
DLC[3:0]
DB[7:0]
Field
Field
7:0
3:0
Reset:
Reset:
W
R
W
Figure 10-34. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
R
Data bits 7:0
Data Length Code Bits — The data length code contains the number of bytes (data byte count) of the respective
message. During the transmission of a remote frame, the data length code is transmitted as programmed while
the number of transmitted data bytes is always 0. The data byte count ranges from 0 to 8 for a data frame.
Table 10-33
Data Length Register (DLR)
0x0005 (DSR1)
0x0006 (DSR2)
0x0007 (DSR3)
0x0008 (DSR4)
0x0009 (DSR5)
0x000A (DSR6)
0x000B (DSR7)
Figure 10-35. Data Length Register (DLR) — Extended Identifier Mapping
x
7
DB7
7
x
shows the effect of setting the DLC bits.
= Unused; always read “x”
Table 10-31. DSR0–DSR7 Register Field Descriptions
6
x
DB6
6
x
Table 10-32. DLR Register Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
5
x
DB5
x
5
4
x
DB4
Description
Description
x
4
DLC3
3
x
DB3
x
3
DLC2
x
DB2
2
x
2
Freescale Semiconductor
DLC1
x
DB1
1
1
x
DLC0
x
DB0
0
0
x