MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 728

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
19.4.7.2
Breakpoints can be generated when internal comparator channels trigger the state sequencer to the final
state. If configured for tagging, then the breakpoint is generated when the tagged opcode reaches the
execution stage of the instruction queue. If an end aligned trigger is selected or no tracing is enabled,
breakpoints can be generated immediately, depending on the state of the DBGBRK[n] bits.
If a begin or mid aligned tracing session is selected by the TSOURCE bits, breakpoints are requested when
the tracing session has completed, thus the breakpoint is requested only on completion of the subsequent
trace (see
immediately independent of tracing trigger alignment.
19.4.7.3
If a TRIG triggers occur, the final state is entered. Tracing trigger alignment is defined by the TALIGN
bits. If a tracing session is selected by the TSOURCE bits, breakpoints are requested when the tracing
session has completed, thus if begin or mid aligned triggering is selected, the breakpoint is requested only
on completion of the subsequent trace. If no tracing session is selected, breakpoints are requested
immediately. TRIG breakpoints are possible even if the DBG module is disarmed. TRIG bit breakpoints
are enabled by setting DBGBRK[n].
19.4.7.4
Tagging using the external TAGHI/TAGLO pins always ends the session immediately at the tag hit. It is
always end aligned, independent of internal channel trigger alignment configuration. External tag
breakpoints are always mapped to the CPU, are only possible in emulation modes and can be enabled by
setting DBGBRK[1].
730
BRK
0
0
0
0
0
0
1
1
x
00,01,10
00,01,10
TALIGN
Table
00
00
01
01
10
10
11
Breakpoints via TAGHI Or TAGLO Pin Taghits
Breakpoints From Internal Comparator Channel Final State Triggers
Breakpoints Generated Via The TRIG Bit
19-44). If the BRK bit is set on the triggering channel, then the breakpoint is generated
DBGBRK[n]
Table 19-44. Setup for Both XGATE and CPU Breakpoints
0
1
0
1
0
1
0
1
x
MC9S12XDP512 Data Sheet, Rev. 2.21
Terminate tracing and generate breakpoint immediately on trigger
Fill trace buffer until trigger, then a breakpoint request occurs
Terminate tracing immediately on trigger without breakpoint
Request breakpoint after the 32 further trace buffer entries
A breakpoint request occurs when trace buffer is full
End tracing 32 line entries after trigger
End tracing 32 line entries after trigger
(no breakpoints — keep running)
(no breakpoints — keep running)
(no breakpoints — keep running)
Fill trace buffer until trigger
Start trace buffer at trigger
Start trace buffer at trigger
Start trace buffer at trigger
Start trace buffer at trigger
Type of Debug Session
Reserved
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