MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 729

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.4.7.5
XGATE software breakpoints have the highest priority. Active tracing sessions are terminated
immediately.
If a TRIG triggers occur after begin or mid aligned tracing has already been triggered by a comparator
instigated transition to final state, then TRIG no longer has an effect. When the associated tracing session
is complete, the breakpoint occurs. Similarly if a TRIG is followed by a subsequent trigger from a
comparator channel whose BRK=0, it has no effect, since tracing has already started.
If a comparator tag hit occurs simultaneously with an external TAGHI/TAGLO hit, the state sequencer
enters State0. TAGHI/TAGLO triggers are always end aligned, to end tracing immediately, independent of
the tracing trigger alignment bits TALIGN[1:0].
19.4.7.5.1
Breakpoint operation is dependent on the state of the BDM module. If the BDM module is active, the CPU
is executing out of BDM firmware and S12X breakpoints are disabled. In addition, while executing a BDM
TRACE command, tagging into BDM is disabled.
If BDM is not active, the breakpoint will give priority to BDM requests over SWI requests if the breakpoint
happens to coincide with a SWI instruction in the user’s code. On returning from BDM, the SWI from user
code gets executed.
BDM cannot be entered from a breakpoint unless the ENABLE bit is set in the BDM. If entry to BDM via
a BGND instruction is attempted and the ENABLE bit in the BDM is cleared, the CPU actually executes
the BDM firmware code. It checks the ENABLE and returns if ENABLE is not set. If not serviced by the
monitor then the breakpoint is re-asserted when the BDM returns to normal CPU flow.
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
and DBG breakpoint could occur simultaneously. The CPU ensures that BDM requests have a higher
priority than SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid
re-triggering a breakpoint.
Freescale Semiconductor
(DBGC1[3])
DBGBRK[1]
1
2
3
The DBGC1[4] bit (BDM) must be set if using the BDM interface together with the DBG module. Failure to set this bit could
End aligned tagged Breakpoint to SWI. Begin, Mid aligned and Forced Breakpoints disabled
All sources except XGATE software BKP, which are independent of this bit.
result in XGATE generated breakpoints to SWI during BDM firmware execution corrupting the S12X PC return address,
should the user have entered BDM via the BACKGROUND command or BGND instruction.
0
1
1
1
1
1
1
DBG Breakpoint Priorities
(DBGC1[4])
DBG Breakpoint priorities, mapping and BDM interfacing
BDM bit
X
0
0
1
1
1
enabled
Table 19-45. Breakpoint Mapping Summary
BDM
X
0
1
0
1
1
MC9S12XDP512 Data Sheet, Rev. 2.21
BDM active
X
X
0
0
0
1
Illegal Configuration. Do Not Use.
Illegal Configuration. Do Not Use.
Type of Debug Session
Chapter 19 S12X Debug (S12XDBGV2) Module
Breakpoint to BDM
Breakpoint to SWI
No Breakpoint
No Breakpoint
2
3
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