MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 828

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.5
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.6
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
830
PC[7:0]
PD[7:0]
Reset
Reset
Field
Field
Exp.:
Exp.:
7–0
7–0
W
W
R
R
DATA15
DATA7
PC7
Port C — Port C pins 7–0 are associated with data I/O lines DATA15 through DATA8 respectively in expanded
modes. When this port is not used for external data, these pins can be used as general purpose I/O. If the data
direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,
otherwise the buffered pin input state is read.
PD7
Port D — Port D pins 7–0 are associated with data I/O lines DATA7 through DATA0 respectively in expanded
modes. When this port is not used for external data, these pins can be used as general purpose I/O. — If the
data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port register,
otherwise the buffered pin input state is read.
Port C Data Register (PORTC)
Port D Data Register (PORTD)
0
0
7
7
DATA14
DATA6
PC6
PD6
0
0
6
6
Figure 22-7. Port C Data Register (PORTC)
Figure 22-8. Port D Data Register (PORTD)
Table 22-8. PORTC Field Descriptions
Table 22-9. PORTD Field Descriptions
DATA13
MC9S12XDP512 Data Sheet, Rev. 2.21
DATA5
PC5
PD5
0
0
5
5
DATA12
DATA4
PC4
PD4
0
0
4
4
Description
Description
DATA11
DATA3
PC3
PD3
0
0
3
3
DATA10
DATA2
PC2
PD2
0
0
2
2
Freescale Semiconductor
DATA9
DATA1
PC1
PD1
0
0
1
1
DATA8
DATA0
PC0
PD0
0
0
0
0