MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 5

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Revision History
Freescale Semiconductor
October 2005
October 2009
August 2008
September
April, 2005
June 2006
June 2007
May, 2005
May, 2005
April 2008
May 2005
May 2006
July 2005
July 2006
July 2007
2009
Date
Revision
Level
02.07
02.08
02.09
02.10
02.11
02.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
MC9S12XDP512 Data Sheet, Rev. 2.21
New Book
Minor corrections
removed ESD Machine Model from electrical characteristics
added thermal characteristics
added more details to run current measurement configurations
VDDA supply voltage range 3.15V - 3.6V fot ATD Operating Characteristics
I/O Chararcteristics for alll pins except EXTAL, XTAL ....
corrected VREG electrical spec
IDD wait max 95mA
Improvements to NVM reliabity spec, added part numbers
Added ROM parts to App.
Single Souce S12XD Fam. Document, New Memory Map Figures,
SPI electricals updated
Voltage Regulator electricals updated
Added Partnumbers and 1L15Y maskset
Updated App. E 6SCI’s on 112 pin DT/P512 and 3 SPI’s on all D256 parts
Data Sheet covers S12XD/B & A Family
Included differnt pull device specification for differnt masksets
Minor Corrections and Improvments
Added 2M42E and 1M84E masksets
Modified Appendix
Better explanation of ATD0/1 for S12XD-Family see page 1305
S12XB256 ATD specification changed see Appendix E.6
added M23S maskset
Corrected XGRAMSIZE of S12XD256 on page 44
Corrected 17.4.2.4 XGATE Memory Map Scheme
Corrected 18.4.2.4 XGATE Memory Map Scheme
Corrected Table E-6 , 30K flash memory available for XGATE on B256
Corrected Footnote in Appendix E3 regarding Shared XGATE/CPU area
Description
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