MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 91

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

2.3.2.8
This register selects the timeout period for the real time interrupt.
Read: Anytime
Write: Anytime
Freescale Semiconductor
RTR[6:4]
RTR[3:0]
RTDEC
Reset
SCME
Field
Field
PRE
PCE
6–4
3–0
2
1
0
7
W
R
RTDEC
RTI Enable during Pseudo Stop Bit — PRE enables the RTI during pseudo stop mode. Write anytime.
0 RTI stops running during pseudo stop mode.
1 RTI continues running during pseudo stop mode.
Note: If the PRE bit is cleared the RTI dividers will go static while pseudo stop mode is active. The RTI dividers
COP Enable during Pseudo Stop Bit — PCE enables the COP during pseudo stop mode. Write anytime.
0 COP stops running during pseudo stop mode
1 COP continues running during pseudo stop mode
Note: If the PCE bit is cleared, the COP dividers will go static while pseudo stop mode is active. The COP
Self Clock Mode Enable Bit
Normal modes: Write once
Special modes: Write anytime
SCME can not be cleared while operating in self clock mode (SCM = 1).
0 Detection of crystal clock failure causes clock monitor reset (see
1 Detection of crystal clock failure forces the MCU in self clock mode (see
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See
1 Decimal based divider value. See
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
and
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional
register. The source clock for the RTI is OSCCLK.
CRG RTI Control Register (RTICTL)
0
7
A write to this register initializes the RTI counter.
Table
will not initialize like in wait mode with RTIWAI bit set.
dividers will not initialize like in wait mode with COPWAI bit set.
2-8.
RTR6
0
6
granularity.Table 2-7
Table 2-5. PLLCTL Field Descriptions (continued)
Figure 2-11. CRG RTI Control Register (RTICTL)
Table 2-6. RTICTL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
RTR5
0
5
Table 2-7
Table 2-8
and
RTR4
NOTE
Table 2-8
0
4
Description
Description
show all possible divide values selectable by the RTICTL
RTR3
0
3
Chapter 2 Clocks and Reset Generator (S12CRGV6)
Section 2.5.2, “Clock Monitor
RTR2
0
2
Section 2.4.2.2, “Self Clock
RTR1
0
1
Reset”).
Table 2-7
RTR0
Mode”).
0
0
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