MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 827

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.3
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.4
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Freescale Semiconductor
DDRA[7:0]
DDRB[7:0]
Reset
Reset
Field
Field
7–0
7–0
W
W
R
R
DDRA7
DDRB7
Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general
purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general
purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
Port A Data Direction Register (DDRA)
Port B Data Direction Register (DDRB)
0
0
7
7
on PORTA after changing the DDRA register.
on PORTB after changing the DDRB register.
DDRA6
DDRB6
0
0
6
6
Figure 22-5. Port A Data Direction Register (DDRA)
Figure 22-6. Port B Data Direction Register (DDRB)
Table 22-6. DDRA Field Descriptions
Table 22-7. DDRB Field Descriptions
DDRA5
DDRB5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
DDRA4
DDRB4
0
0
4
4
Description
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
DDRA3
DDRB3
0
0
3
3
DDRA2
DDRB2
0
0
2
2
DDRA1
DDRB1
0
0
1
1
DDRA0
DDRB0
0
0
0
0
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