MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 674

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.4.2.1.1
Expansion of the CPU Local Address Map
The program page index register in MMC allows accessing up to 4 Mbyte of FLASH or ROM in the global
memory map by using the eight page index bits to page 256 16 Kbyte blocks into the program page
window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
The page value for the program page window is stored in the PPAGE register. The value of the PPAGE
register can be read or written by normal memory accesses as well as by the CALL and RTC instructions
(see
Control registers, vector space and parts of the on-chip memories are located in unpaged portions of the
64-kilobyte local CPU address space.
The starting address of an interrupt service routine must be located in unpaged memory unless the user is
certain that the PPAGE register will be set to the appropriate value when the service routine is called.
However an interrupt service routine can call other routines that are in paged memory. The upper
16-kilobyte block of the local CPU memory space (0xC000–0xFFFF) is unpaged. It is recommended that
all reset and interrupt vectors point to locations in this area or to the other unpaged sections of the local
CPU memory map.
Table 18-19 Table 18-12
address, the PPAGE register value and value of the ROMHM bit in the MMCCTL1 register.
The RAM page index register allows accessing up to 1 Mbyte –2 Kbytes of RAM in the global memory
map by using the eight RPAGE index bits to page 4 Kbyte blocks into the RAM page window located in
the local CPU memory space from address 0x1000 to address 0x1FFF. The EEPROM page index register
EPAGE allows accessing up to 256 Kbytes of EEPROM in the system by using the eight EPAGE index
bits to page 1 Kbyte blocks into the EEPROM page window located in the local CPU memory space from
address 0x0800 to address 0x0BFF.
674
Section 18.5.1, “CALL and RTC
Expansion of the Local Address Map
1
The internal or the external bus is accessed based on the size of the memory resources
implemented on-chip. Please refer to
0xC000–0xFFFF
0x8000–0xBFFF
0x4000–0x7FFF
CPU Address
Local
summarizes mapping of the address bus in Flash/External space based on the
Table 18-19. Global FLASH/ROM Allocated
MC9S12XDP512 Data Sheet, Rev. 2.21
ROMHM
Instructions).
N/A
N/A
N/A
0
1
Figure 1-23
External
Access
Yes
No
Yes
No
No
1
1
for further details.
0x7F_4000 –0x7F_7FFF
0x7F_C000–0x7F_FFFF
0x40_0000–0x7F_FFFF
0x14_4000–0x14_7FFF
Global Address
Freescale Semiconductor