MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 89

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

2.3.2.6
This register controls CRG clock selection. Refer to
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
COPWAI
PLLSEL
PLLWAI
RTIWAI
Reset
PSTP
Field
7
6
3
1
0
W
R
PLLSEL
PLL Select Bit — Write anytime. Writing a1 when LOCK = 0 and AUTO = 1, or TRACK = 0 and AUTO = 0 has
no effect This prevents the selection of an unstable PLLCLK as SYSCLK. PLLSEL bit is cleared when the MCU
enters self clock mode, Stop mode or wait mode with PLLWAI bit set.
0 System clocks are derived from OSCCLK (Bus Clock = OSCCLK / 2).
1 System clocks are derived from PLLCLK (Bus Clock = PLLCLK / 2).
Pseudo Stop Bit
Write: Anytime
This bit controls the functionality of the oscillator during stop mode.
0 Oscillator is disabled in stop mode.
1 Oscillator continues to run in stop mode (pseudo stop).
Note: Pseudo stop mode allows for faster STOP recovery and reduces the mechanical stress and aging of the
PLL Stops in Wait Mode Bit
Write: Anytime
If PLLWAI is set, the CRG will clear the PLLSEL bit before entering wait mode. The PLLON bit remains set during
wait mode, but the PLL is powered down. Upon exiting wait mode, the PLLSEL bit has to be set manually if PLL
clock is required.
While the PLLWAI bit is set, the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected
target frequency after exiting wait mode.
0 PLL keeps running in wait mode.
1 PLL stops in wait mode.
RTI Stops in Wait Mode Bit
Write: Anytime
0 RTI keeps running in wait mode.
1 RTI stops and initializes the RTI dividers whenever the part goes into wait mode.
COP Stops in Wait Mode Bit
Normal modes: Write once
Special modes: Write anytime
0 COP keeps running in wait mode.
1 COP stops and initializes the COP counter whenever the part goes into wait mode.
CRG Clock Select Register (CLKSEL)
0
7
resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption.
= Unimplemented or Reserved
PSTP
0
6
Figure 2-9. CRG Clock Select Register (CLKSEL)
Table 2-4. CLKSEL Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
0
0
4
Figure 2-17
Description
PLLWAI
0
3
Chapter 2 Clocks and Reset Generator (S12CRGV6)
for more details on the effect of each bit.
0
0
2
RTIWAI
0
1
COPWAI
0
0
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