MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 347

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

7.3.2.29
Read: Anytime.
Write: Has no effect.
All bits reset to zero.
These registers are used to latch the value of the corresponding pulse accumulator when the related bits in
register ICPAR are enabled (see
Freescale Semiconductor
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
PA3H7
PA2H7
PA1H7
PA0H7
8-Bit Pulse Accumulators Holding Registers (PA3H–PA0H)
0
0
0
0
7
7
7
7
Figure 7-51. 8-Bit Pulse Accumulators Holding Register 3 (PA3H)
Figure 7-52. 8-Bit Pulse Accumulators Holding Register 2 (PA2H)
Figure 7-53. 8-Bit Pulse Accumulators Holding Register 1 (PA1H)
Figure 7-54. 8-Bit Pulse Accumulators Holding Register 0 (PA0H)
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
PA3H6
PA2H6
PA1H6
PA0H6
0
0
0
0
6
6
6
6
Section 7.4.1.3, “Pulse
PA3H5
PA2H5
PA1H5
PA0H5
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
0
5
5
5
5
PA3H4
PA2H4
PA1H4
PA0H4
0
0
0
0
4
4
4
4
Accumulators”).
PA3H3
PA2H3
PA1H3
PA0H3
Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
0
0
0
0
3
3
3
3
PA3H2
PA2H2
PA1H2
PA0H2
0
0
0
0
2
2
2
2
PA3H1
PA2H1
PA1H1
PA0H1
0
0
0
0
1
1
1
1
PA3H0
PA2H0
PA1H0
PA0H0
0
0
0
0
0
0
0
0
347