MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 97

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

2.3.2.12
This register is used to restart the COP time-out period.
Read: Always reads 0x_00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
Freescale Semiconductor
Reset
W
R
Writing any value other than 0x_55 or 0x_AA causes a COP reset. To restart the COP time-out
period you must write 0x_55 followed by a write of 0x_AA. Other instructions may be executed
between these writes but the sequence (0x_55, 0x_AA) must be completed prior to COP end of
time-out period to avoid a COP reset. Sequences of 0x_55 writes or sequences of 0x_AA writes
are allowed. When the WCOP bit is set, 0x_55 and 0x_AA writes must be done in the last 25% of
the selected time-out period; writing any value in the first 75% of the selected period will cause a
COP reset.
Bit 7
CRG COP Timer Arm/Reset Register (ARMCOP)
0
0
7
Bit 6
0
0
6
Figure 2-15. ARMCOP Register Diagram
MC9S12XDP512 Data Sheet, Rev. 2.21
Bit 5
0
0
5
Bit 4
0
0
4
Bit 3
0
0
3
Chapter 2 Clocks and Reset Generator (S12CRGV6)
Bit 2
0
0
2
Bit 1
0
0
1
Bit 0
0
0
0
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