MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 750

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.2
Read: Anytime
Write: Never
752
Address: 0x0021
SSF[2:0]
Reset
EXTF
Field
POR
TBF
2–0
7
6
W
R
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits CNT[6:0].
The TBF bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset
initialization. Other system generated resets have no affect on this bit
External Tag Hit Flag — The EXTF bit indicates if a tag hit condition from an external TAGHI/TAGLO tag was
met since arming. This bit is cleared when ARM in DBGC1 is written to a one.
0 External tag hit has not occurred
1 External tag hit has occurred
State Sequencer Flag Bits — The SSF bits indicate in which state the State Sequencer is currently in. During
a debug session on each transition to a new state these bits are updated. If the debug session is ended by
software clearing the ARM bit, then these bits retain their value to reflect the last state of the state sequencer
before disarming. If a debug session is ended by an internal trigger, then the state sequencer returns to state0
and these bits are cleared to indicate that state0 was entered during the session. On arming the module the state
sequencer enters state1 and these bits are forced to SSF[2:0] = 001. See
TBF
Debug Status Register (DBGSR)
—
0
7
= Unimplemented or Reserved
EXTF
Table 20-7. SSF[2:0] — State Sequence Flag Bit Encoding
0
0
6
101,110,111
Figure 20-4. Debug Status Register (DBGSR)
SSF[2:0]
000
001
010
011
100
Table 20-6. DBGSR Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
0
5
0
0
0
4
Description
State0 (disarmed)
Current State
Final State
Reserved
0
0
0
3
State1
State2
State3
SSF2
Table 20-7
0
0
2
.
Freescale Semiconductor
SSF1
0
0
1
SSF0
0
0
0