MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 825

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

22.3.2.1
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
22.3.2.2
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Freescale Semiconductor
Function
Function
PA[7:0]
Reset
Reset
Field
7–0
Alt.
Alt.
W
W
R
R
ADDR15
ADDR7
IVD15
IVD7
Port A — Port A pins 7–0 are associated with address outputs ADDR15 through ADDR8 respectively in
expanded modes. When this port is not used for external addresses, these pins can be used as general purpose
I/O. If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
PA7
mux
PB7
mux
Port A Data Register (PORTA)
Port B Data Register (PORTB)
0
0
7
7
ADDR14
ADDR6
IVD14
IVD6
mux
PB6
mux
PA6
0
0
6
6
Figure 22-4. Port B Data Register (PORTB)
Figure 22-3. Port A Data Register (PORTA)
Table 22-4. PORTA Field Descriptions
ADDR13
ADDR5
MC9S12XDP512 Data Sheet, Rev. 2.21
IVD13
IVD5
PB5
PA5
mux
mux
0
0
5
5
ADDR12
ADDR4
IVD12
IVD4
mux
PB4
mux
PA4
0
0
4
4
Description
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
ADDR11
ADDR3
IVD11
IVD3
PB3
PA3
mux
mux
0
0
3
3
ADDR10
ADDR2
IVD10
IVD2
mux
PB2
mux
PA2
0
0
2
2
ADDR9
ADDR1
IVD9
IVD1
PB1
PA1
mux
mux
0
0
1
1
ADDR8
ADDR0
IVD8
IVD0
UDS
mux
PB0
mux
PA0
or
0
0
0
0
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