MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 621

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

17.3.2.3
Read: Anytime
Write: Anytime
The global page index register is used only when the CPU is executing a global instruction (GLDAA,
GLDAB, GLDD, GLDS, GLDX, GLDY,GSTAA, GSTAB, GSTD, GSTS, GSTX, GSTY) (see CPU Block
Guide). The generated global address is the result of concatenation of the CPU local address [15:0] with
the GPAGE register [22:16] (see
Freescale Semiconductor
Address: 0x0010
GP[6:0]
Reset
Field
6–0
W
R
Bit22
LDAADR
MOVB
GLDAA
Global Page Index Bits 6–0 — These page index bits are used to select which of the 128 64-kilobyte pages is
to be accessed.
Global Page Index Register (GPAGE)
0
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
Example 17-1. This example demonstrates usage of the GPAGE register
GPAGE Register [6:0]
EQU $5000
#$14, GPAGE
>LDAADR
= Unimplemented or Reserved
GP6
0
6
Figure 17-6. Global Page Index Register (GPAGE)
Figure
Figure 17-7. GPAGE Address Mapping
Table 17-7. GPAGE Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
GP5
0
5
;Initialize LDADDR to the value of $5000
;Initialize GPAGE register with the value of $14
;Load Accu A from the global address $14_5000
1-7).
Global Address [22:0]
Bit16
CAUTION
Bit15
GP4
0
4
Description
GP3
0
3
CPU Address [15:0]
Chapter 17 Memory Mapping Control (S12XMMCV2)
GP2
0
2
GP1
0
1
Bit 0
GP0
0
0
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