M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 100

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

FLASH EEPROM
8.3.1 FLASH EEPROM Lock Control Register
In normal modes, the LOCK bit can be written only once after reset.
LOCK — Lock Register Bit
8.3.2 FLASH EEPROM Module Configuration Register
This register controls the operation of the FLASH EEPROM array. BOOTP cannot be changed when the
LOCK control bit in the FEELCK register is set or if ENPE in the FEECTL register is set.
The boot block is located at $7800–$7FFF or $F800–$FFFF, depending upon the mapped location of the
FLASH EEPROM array and mask set ($7C00–$7FFF or $FC00–$FFFF for 1-Kbyte block).
BOOTP — Boot Protect Bit
8.3.3 FLASH EEPROM Module Test Register
In normal mode, writes to FEETST control bits have no effect and always read 0. The FLASH EEPROM
module cannot be placed in test mode inadvertently during normal operation.
FSTE — Stress Test Enable Bit
100
0 = Enable write to FEEMCR register.
1 = Disable write to FEEMCR register.
0 = Enable erase and program of 1-Kbyte or 2-Kbyte boot block.
1 = Disable erase and program of 1-Kbyte or 2-Kbyte boot block.
0 = Disables the gate/drain stress circuitry
1 = Enables the gate/drain stress circuitry
Figure 8-2. FLASH EEPROM Module Configuration Register (FEEMCR)
Address: $00F4
Address: $00F5
Address: $00F6
Reset:
Reset:
Reset:
Read:
Write:
Read:
Write:
Read:
Write:
Figure 8-1. FLASH EEPROM Lock Control Register (FEELCK)
Figure 8-3. FLASH EEPROM Module Test Register (FEETST)
FSTE
Bit 7
Bit 7
Bit 7
0
0
0
0
0
GADR
M68HC12B Family Data Sheet, Rev. 9.1
6
0
0
6
0
0
6
0
HVT
5
0
0
5
0
0
5
0
FENLV
4
0
0
4
0
0
4
0
FDISVFP
3
0
0
3
0
0
3
0
VTCK
2
0
0
2
0
0
2
0
STRE
1
0
1
0
1
0
0
0
Freescale Semiconductor
BOOTP
MWPR
LOCK
Bit 0
Bit 0
Bit 0
0
1
0