M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 73

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

4.7.7 Other Resources
The timer, serial communications interface (SCI), serial peripheral interface (SPI), byte data link controller
(BDLC), pulse-width modulator (PWM), analog-to-digital converter (ATD), and MSCAN are off after reset.
4.8 Interrupt Recognition
Once enabled, an interrupt request can be recognized at any time after the I bit in the CCR is cleared.
When an interrupt request is recognized, the CPU responds at the completion of the instruction being
executed. Interrupt latency varies according to the number of cycles required to complete the instruction.
Some of the longer instructions can be interrupted and resume normally after servicing the interrupt.
When the CPU begins to service an interrupt request, it:
After stacking the CCR, the CPU:
If no other interrupt request is pending at the end of the interrupt service routine, a return-from-interrupt
(RTI) instruction recovers the stacked values. Program execution resumes program at the return address.
If another interrupt request is pending at the end of an interrupt service routine, the RTI instruction
recovers the stacked values. However, the CPU then:
Freescale Semiconductor
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Clears the instruction queue
Calculates the return address
Stacks the return address and the contents of the CPU registers as shown in
Sets the I bit to prevent other interrupts from disrupting the interrupt service routine
Sets the X bit if an XIRQ interrupt request is pending
Fetches the interrupt vector for the highest-priority request that was pending at the beginning of the
interrupt sequence
Begins execution of the interrupt service routine at the location pointed to by the vector
Adjusts the stack pointer to point again at the stacked CCR location, SP – 9
Fetches the vector of the pending interrupt
Begins execution of the interrupt service routine at the location pointed to by the vector
Table 4-3. Stacking Order on Entry to Interrupts
Memory Location
SP – 2
SP – 4
SP – 6
SP – 8
SP – 9
M68HC12B Family Data Sheet, Rev. 9.1
Stacked Values
RTN
Y
X
B : A
CCR
H
H
H
: RTN
: Y
: X
L
L
L
Table 4-3
Interrupt Recognition
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