M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 282

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Analog-to-Digital Converter (ATD)
17.3.6 ATD Control Register 5
Read: Anytime
Write: Anytime
The ATD control register 5 is used to select the conversion modes, the conversion channel(s), and initiate
conversions.
A write to ATDCTL5 initiates a new conversion sequence. If a conversion sequence is in progress when
a write occurs, that sequence is aborted and the SCF and CCF bits are reset.
S8CM — Select 8 Channel Mode Bit
282
Clearing these bits causes the prescale value to default to 1 which results in a divide-by-two prescale
factor. This signal is then fed into the divide-by-two logic. The reset state divides the P clock by a total
of four and is appropriate for nominal operation at a bus rate of between 2 MHz and 8 MHz.
shows the divide-by operation and the appropriate range of system clock frequencies.
0 = Conversion sequence consists of four conversions.
1 = Conversion sequence consists of eight conversions.
Reset:
Address: $0065
Read:
Write:
1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value becomes
2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value becomes
Prescale Value
maximum conversion rate that can be used on this ATD module.
minimum conversion rate that this ATD can perform.
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
1xxxx
Bit 7
0
Figure 17-7. ATD Control Register 5 (ATDCTL5)
= Unimplemented
S8CM
Table 17-3. Clock Prescaler Values
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Total Divisor
SCAN
10
12
14
16
2
4
6
8
5
0
MULT
4
0
Max P Clock
Do not use
4 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
8 MHz
CD
3
0
(1)
CC
2
0
Min P Clock
1 MHz
2 MHz
3 MHz
4 MHz
5 MHz
6 MHz
7 MHz
8 MHz
CB
1
0
Freescale Semiconductor
(2)
Bit 0
CA
0
Table 17-3