M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 233

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

15.9.2 BDLC Control Register 2
This register controls transmitter operations of the BDLC.
ALOOP — Analog Loopback Mode Bit
DLOOP — Digital Loopback Mode Bit
Freescale Semiconductor
This bit determines if the J1850 bus is driven by the analog physical interface’s final drive stage. The
programmer places the transceiver into loopback mode first, then sets ALOOP which resets the BDLC
state machine to a known state. When the user clears ALOOP, to indicate the transceiver has been
taken out of loopback mode, the BDLC waits for an EOF symbol before attempting to transmit. Most
transceivers have the ALOOP feature available.
This bit determines the source to which the BDLC internal digital receive input is connected and can
be used to isolate bus fault conditions. If a fault condition has been detected on the bus, this control
bit allows the programmer to connect the digital transmit output to the digital receive input. In this
configuration, data sent from the transmit buffer is reflected back into the receive buffer. If no faults
exist in the BDLC, the fault is in the physical interface block or elsewhere on the J1850 bus. When the
DLOOP bit is set, the BDLC is disengaged from the J1850 bus. Therefore, the BDLC does not receive
an edge from the J1850 bus which would normally cause a BSVR non-maskable wakeup interrupt.
1 = Input to the analog physical interface’s final drive stage is looped back to the BDLC receiver.
0 = BDLC digital circuitry drives an output for the J1850 bus. After the bit is cleared, the BDLC
1 = BDRxD is connected to BDTxD. The BDLC is in digital loopback mode.
0 = BDTxD is not connected to BDRxD. The BDLC is taken out of digital loopback mode and can
The J1850 bus is not driven.
requires the bus to be idle for a minimum of end-of-frame symbol time (t
reception or a minimum of inter-frame symbol time (t
now drive or receive the J1850 bus normally (given ALOOP is not set). After clearing DLOOP,
the BDLC requires the bus to be idle for a minimum of end-of-frame symbol (t
allowing reception of a message. The BDLC requires the bus to be idle for a minimum of
inter-frame separator symbol (t
Address: $00FA
The DLOOP bit is a fault condition aid and should never be altered after the
BDR is loaded for transmission. Changing DLOOP during a transmission
may cause corrupted data to be transmitted onto the J1850 network.
Before going into digital loopback mode, the RXPOL bit in the BARD
register must be set so that the receive polarity is not expected to be
inverted.
Reset:
Read:
Write:
ALOOP
Bit 7
1
Figure 15-13. BDLC Control Register 2 (BCR2)
DLOOP
M68HC12B Family Data Sheet, Rev. 9.1
6
1
tv6
RX4XE
) time before allowing a message to be transmitted.
5
0
NOTE
NBFS
4
0
TEOD
3
0
TRV6
) before message transmission.
TSIFR
2
0
TMIFR1
1
0
TRV4
) before message
TMIFR0
Bit 0
tv4
0
BDLC Registers
) time before
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