M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 288

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Analog-to-Digital Converter (ATD)
; ----------------------------------------------------------------------
;
; ----------------------------------------------------------------------
;
MAIN:
DONE:
breakpoint
; ----------------------------------------------
;
; ----------------------------------------------
INIT:
interrupts
; ----------------------------------------------
;
; ----------------------------------------------
; Set-up ATD, make single conversion and store the result to a memory location.
; Configure and start A/D conversion
; Analog Input Signal: On PORT AD6
; Convert: using single channel, non-continuous
; The result will be located in ADR2H
CONVERT:
;
;
WTCONV:
;
;* -------------------------------
;*
;* -------------------------------
; Delay Required for ATD converter to Stabilize (100 uSec)
DELAY:
288
Subroutine DELAY 100 uS
ORG
BSR
BSR
BRA
LDAA
STAA
BSR
LDAA
STAA
LDAA
STAA
RTS
LDAA
STAA
BRCLR
LDD
BRA
RTS
LDAA
DECA
BNE
RTS
END
MAIN PROGRAM
Subroutine INIT: Initialize ATD
Subroutine CONVERT:
$7000
INIT
CONVERT
DONE
#$80
ATDCTL2
DELAY
#$00
ATDCTL3
#$01
ATDCTL4
#$06
ATDCTL5
ATDSTATH,#$80,WTCONV ; Wait for Sequence Complete Flag
ADR2H
CONVERT
#$C8
DELAY
M68HC12B Family Data Sheet, Rev. 9.1
*
; 16K On-Board RAM, User code data area,
; Branch to INIT subroutine to Initialize ATD
; Branch to CONVERT Subroutine for conversion
; Branch to Self, Convenient place for
; Allow ATD to function normally,
; ATD Flags clear normally & disable
; Delay (100 uS) for WAIT delay time.
; Select continue conversion in BGND Mode
; Ignore FREEZE in ATDCTL3
; Select Final Sample time = 2 A/D clocks
; Prescaler = Div by 4 (PRS4:0 = 1)
; Return from subroutine
; Initializes ATD SCAN=0,MULT=0, PAD6,
; Write Clears Flag
; 4 conversions on a Single Conversion
; sequence,
; Loads conversion result(ADR2H)
; into Accumulator
; Continuously updates results
; Return from subroutine
; Load Accumulator with "100 uSec delay value"
; Decrement ACC
; Branch if not equal to Zero
; Return from subroutine
; End of program
start main program at $7000
;
;
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