M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 195

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

14.2.3.2 SCI Control Register 1
Read: Anytime
Write: Anytime
LOOPS — SCI LOOP Mode/Single-Wire Mode Enable Bit
WOMS — Wired-OR Mode for Serial Pins
Freescale Semiconductor
The receiver input is determined by the RSRC bit. The transmitter output is controlled by the
associated DDRS bit. Both the transmitter and the receiver must be enabled to use the LOOP or the
single-wire mode.
If the DDRS bit associated with the TXD pin is set during the LOOPS = 1, the TXD pin outputs the SCI
waveform. If the DDRS bit associated with the TXD pin is clear during the LOOPS = 1, the TXD pin
becomes high (IDLE line state) for RSRC = 0 and high impedance for RSRC = 1. Refer to
This bit controls the two pins (TXD and RXD) associated with the SCIx section.
0 = SCI transmit and receive sections operate normally.
1 = SCI receive section is disconnected from the RXD pin and the RXD pin is available as
0 = Pins operate in a normal mode with both high and low drive capability. To affect the RXD bit,
1 = Each pin operates in an open drain fashion if that pin is declared as an output.
general-purpose I/O.
that bit would have to be configured as an output (via DDS0/2) which is the single-wire case
when using the SCI. WOMS bit still affects general-purpose output on TXD and RXD pins when
SCIx is not using these pins.
Address:
LOOP
Reset:
Read:
Write:
S
0
1
1
1
1
1
1
$00C2
LOOPS
Bit 7
RSR
0
C
0
0
0
1
1
1
x
Figure 14-5. SCI Control Register 1 (SC0CR1)
DDS1
WOMS
Table 14-2. Loop Mode Functions
x
0
1
1
0
1
1
M68HC12B Family Data Sheet, Rev. 9.1
6
0
WOM
RSRC
0/1
S
0
1
0
1
x
x
5
0
Normal operations
LOOP mode without TXD output
(TXD = high impedance)
LOOP mode with TXD output (CMOS)
LOOP mode with TXD output (open-drain)
Single-wire mode without TXD output
(pin is used as receiver input only,
TXD = high Impedance)
Single-wire mode with TXD output
(The output is also fed back to receiver
input, CMOS.)
Single wire mode for the receiving and
transmitting (open-drain)
M
4
0
Function of Port S Bit 1/3
WAKE
3
0
ILT
Serial Communication Interface (SCI)
2
0
PE
1
0
Bit 0
PT
0
Table
14-2.
195