M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 76

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Operating Modes and Resource Mapping
5.2.1 Normal Operating Modes
These modes provide three operating configurations. Background debugging is available in all three
modes, but must first be enabled for some operations by means of a BDM command. BDM can then be
made active by another BDM command.
5.2.1.1 Normal Expanded Wide Mode
The 16-bit external address and data buses use ports A and B. ADDR15–ADDR8 and DATA15–DATA8
are multiplexed on port A. ADDR7–ADDR0 and DATA7–DATA0 are multiplexed on port B.
5.2.1.2 Normal Expanded Narrow Mode
The 16-bit external address bus uses port A for the high byte and port B for the low byte. The 8-bit external
data bus uses port A. ADDR15–ADDR8 and DATA7–DATA0 are multiplexed on port A.
5.2.1.3 Normal Single-Chip Mode
Normal single-chip mode has no external buses. Ports A, B, and E are configured for general-purpose
input/output (I/O). Port E bits 1 and 0 are input only with internal pullups and the other 22 pins are
bidirectional I/O pins that are initially configured as high-impedance inputs. Port E pullups are enabled on
reset. Port A and B pullups are disabled on reset.
5.2.2 Special Operating Modes
Special operating modes are commonly used in factory testing and system development.
5.2.2.1 Special Expanded Wide Mode
This mode is for emulation of normal expanded wide mode and emulation of normal single-chip mode with
a 16-bit bus. The bus-control pins of port E are all configured for their bus-control output functions rather
than general-purpose I/O.
5.2.2.2 Special Expanded Narrow Mode
This mode is for emulation of normal expanded narrow mode. External 16-bit data is handled as two
back-to-back bus cycles, one for the high byte followed by one for the low byte. Internal operations
continue to use full 16-bit data paths.
5.2.2.3 Special Single-Chip Mode
This mode can be used to force the MCU to active BDM mode to allow system debug through the BKGD
pin. The MCU does not fetch the reset vector and execute application code as it would in other modes.
Instead, the active background mode is in control of CPU execution and BDM firmware waits for additional
serial commands through the BKGD pin. There are no external address and data buses in this mode. The
MCU operates as a stand-alone device and all program and data space are on-chip. External port pins
can be used for general-purpose I/O.
M68HC12B Family Data Sheet, Rev. 9.1
76
Freescale Semiconductor