M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 250

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

16.5 Interrupts
The msCAN12 supports four interrupt vectors mapped onto 11 different interrupt sources, any of which
can be individually masked. For details, see
msCAN12 Transmitter Control
16.5.1 Interrupt Acknowledge
Interrupts are associated directly with one or more status flags in either the msCAN12 receiver flag
register (CRFLG) or the msCAN12 transmitter control register (CTCR). Interrupts are pending as long as
one of the corresponding flags is set. The flags in the aforementioned registers must be reset within the
interrupt handler to handshake the interrupt. The flags are reset through writing a 1 to the corresponding
bit position. A flag cannot be cleared if the respective condition still prevails.
16.5.2 Interrupt Vectors
The msCAN12 supports four interrupt vectors as shown in
dependent on the chip integration and to be defined. The relative interrupt priority is also integration
dependent and to be defined.
250
msCAN12 Controller
1. Transmit interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be
2. Receive interrupt: A message has been successfully received and loaded into the foreground
3. Wakeup interrupt: An activity on the CAN bus occurred during msCAN12 internal sleep mode.
4. Error interrupt: An overrun, error, or warning condition occurred. The receiver flag register
loaded to schedule a message for transmission. The empty message buffers TXE flags are set.
receive buffer. This interrupt will be emitted immediately after receiving the end of frame (EOF)
symbol. The RXF flag is set.
(CRFLG) will indicate one of these conditions:
–
–
–
–
–
–
Overrun: An overrun condition as described in
Receiver warning: The receive error counter has reached the CPU warning limit of 96.
Transmitter warning: The transmit error counter has reached the CPU warning limit of 96.
Receiver error passive: The receive error counter has exceeded the error passive limit of 127
and msCAN12 has gone to error passive state.
Transmitter error passive: The transmit error counter has exceeded the error passive limit of
127 and msCAN12 has gone to error passive state.
Bus off: The transmit error counter has exceeded 255 and msCAN12 has gone to bus-off state.
Bit manipulation instructions (BSET) must not be used to clear interrupt
flags.
Register.
M68HC12B Family Data Sheet, Rev. 9.1
16.12.5 msCAN12 Receiver Flag Register
NOTE
16.3.2 Receive Structures
Table
16-1. The vector addresses are
Freescale Semiconductor
has occurred.
to
16.12.8