M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 265

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

16.12.4 msCAN12 Bus Timing Register 1
SAMP — Sampling Bit
TSEG22–TSEG10 — Time Segment Bits
1. In this case, PHASE_SEG1 must be at least two times quanta.
Freescale Semiconductor
This bit determines the number of samples of the serial bus to be taken per bit time. If set, three
samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority
rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken
per bit.
Time segments within the bit time fix the number of clock cycles per bit time and the location of the
sample point. See
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in
SYNC_SEG
Transmit point
Sample point
0 = One sample per bit
1 = Three samples per bit.
Address: $0103
Reset:
Read:
Write:
System expects transitions to occur on the bus during this period.
A node in transmit mode will transfer a new value to the CAN bus at this point.
A node in receive mode will sample the bus at this point. If the three samples per bit option is
selected, then this point marks the position of the third sample.
TSEG13
Figure
Figure 16-19. msCAN12 Bus Timing Register 1 (CBTR1)
SAMP
Bit 7
0
0
0
0
1
.
0
16-7.
TSEG22
(1)
TSEG12
TSEG22
6
0
Table 16-7. Time Segment Syntax
Table 16-8. Time Segment Values
M68HC12B Family Data Sheet, Rev. 9.1
0
0
0
0
1
0
0
1
.
.
TSEG21
5
0
TSEG11
TSEG21
0
0
1
1
1
0
0
1
.
.
TSEG20
4
0
TSEG10
TSEG20
TSEG13
0
1
0
1
1
0
1
1
.
.
3
0
Programmer’s Model of Control Registers
TSEG12
16 Tq clock cycles
Time Segment 1
Time Segment 2
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
2 Tq clock cycles
8 Tq clock cycles
1 Tq clock cycle
1 Tq clock cycle
2
0
.
.
TSEG11
1
0
TSEG10
Bit 0
0
Table
16-8.
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