M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 155

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

12.3.15 Data Direction Register for Timer Port
Read: Anytime
Write: Anytime
The timer forces the I/O state to be an output for each timer port pin associated with an enabled output
compare. In these cases the data direction bits will not be changed, but they have no affect on the
direction of these pins. The DDRT will revert to controlling the I/O direction of a pin when the associated
timer output compare is disabled. Input captures do not override the DDRT settings.
12.4 Timer Operation in Modes
Stop — Timer is off since both PCLK and ECLK are stopped.
BDM— Timer keeps running, unless TSBCK = 1.
Wait — Counters keep running, unless TSWAI = 1.
Normal — Timer keeps running, unless TEN = 0.
TEN = 0 —All timer operations are stopped, registers may be accessed.
Gated pulse accumulator ÷64 clock is also disabled.
PAEN = 0 —All pulse accumulator operations are stopped.
Registers may be accessed.
Freescale Semiconductor
0 = Configures the corresponding I/O pin for input only
1 = Configures the corresponding I/O pin for output
Address: $00AF
Reset:
Read:
Write:
Figure 12-29. Data Direction Register for Timer Port (DDRT)
DDT7
Bit 7
0
DDT6
6
0
M68HC12B Family Data Sheet, Rev. 9.1
DDT5
5
0
DDT4
4
0
DDT3
3
0
DDT2
2
0
DDT1
1
0
Timer Operation in Modes
DDT0
Bit 0
0
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