M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 214

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Byte Data Link Communications (BDLC)
15.4 BDLC Operating Modes
The BDLC has five main modes of operation which interact with the power supplies, pins, and rest of the
MCU as shown in
214
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC STOP
Figure
(COP, ILLADDR, PU, RESET, LVR, POR)
ANY MCU RESET SOURCE ASSERTED
Figure 15-2. BDLC Operating Modes State Diagram
15-2.
V
DD
STOP INSTRUCTION OR
WAIT INSTRUCTION AND WCM = 1
≤ V
FROM ANY MODE
DD
(MINIMUM)
Figure 15-1. BDLC Block Diagram
M68HC12B Family Data Sheet, Rev. 9.1
PHYSICAL INTERFACE
POWER OFF
PROTOCOL HANDLER
MUX INTERFACE
CPU INTERFACE
TO J1850 BUS
RESET
RUN
TO CPU
V
ANY MCU RESET SOURCE ASSERTED
DD
NO MCU RESET SOURCE ASSERTED
WAIT INSTRUCTION AND WCM = 0
> V
BDLC
DD
(MINIMUM) AND
NETWORK ACTIVITY OR
OTHER MCU WAKEUP
BDLC WAIT
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