M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 193

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

14.2.1 Data Format
The serial data format requires these conditions:
A frame consists of:
A BREAK is defined as the transmission or reception of a logic 0 for one frame or more.
This SCI supports hardware parity for transmit and receive.
14.2.2 SCI Baud Rate Generation
The basis of the SCI baud rate generator is a 13-bit modulus counter. This counter gives the generator
the flexibility necessary to achieve a reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount of error. The clock source for the
generator comes from the P clock.
Freescale Semiconductor
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An idle-line in the high state before transmission or reception of a message
A start bit (logic 0), transmitted or received, that indicates the start of each character
Data that is transmitted or received least significant bit (LSB) first
A stop bit (logic 1) used to indicate the end of a frame
A start bit
A character of eight or nine data bits
A stop bit
SCI Baud Rate
Desired
14,400
19,200
38,400
1200
2400
4800
9600
110
300
600
Table 14-1. Baud Rate Generation
M68HC12B Family Data Sheet, Rev. 9.1
BR Divisor for
P = 4.0 MHz
2273
833
417
208
104
52
26
17
13
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Serial Communication Interface (SCI)
BR Divisor for
P = 8.0 MHz
4545
1667
833
417
208
104
52
35
26
13
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