M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 328

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M68HC12A4EVB

Manufacturer Part Number
M68HC12A4EVB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of M68HC12A4EVB

Lead Free Status / Rohs Status
Not Compliant
Electrical Specifications
19.17 Serial Peripheral Interface (SPI) Timing
328
Num
1. V
10
11
12
13
1
2
3
4
5
6
7
8
9
and 70% V
DD
= 5.0 Vdc ± 10%, V
Operating frequency
SCK period
Enable lead time
Enable lag time
Clock (SCK) high or low time
Sequential transfer delay
Data setup time (inputs)
Data hold time (inputs)
Slave access time
Slave MISO disable time
Data valid (after SCK edge)
Data hold time (outputs)
Rise Time
Fall Time
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Input
Output
Input
Output
DD
levels, unless otherwise noted.
SS
= 0 Vdc, T
Function
A
= T
M68HC12B Family Data Sheet, Rev. 9.1
(1)
L
to T
H
, 200 pF load on all SPI pins, AC timing is shown with respect to 20% V
Symbol
t
WSCK
t
t
t
t
f
Lead
t
t
SCK
LAG
t
t
t
t
DIS
t
OP
HO
RO
t
TD
SU
t
t
FO
HI
RI
FI
A
V
t
t
cyc
cyc
Min
DC
DC
1/2
1/2
1/2
30
30
30
2
2
1
1
1
0
0
0
− 30
− 30
Freescale Semiconductor
128 t
t
t
cyc
cyc
Max
256
1/2
1/2
50
50
30
30
1
1
−30
−30
cyc
frequency
E-clock
Unit
t
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
sck
cyc
sck
cyc
sck
cyc
cyc
cyc
DD