M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 232

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Byte Data Link Communications (BDLC)
CLKS — Clock Select Bit
R1 and R0 — Rate Select Bits
IE — Interrupt Enable Bit
WCM — Wait Clock Mode Bit
232
For J1850 bus communications to take place, the nominal BDLC operating frequency (f
always be 1.048576 MHz or 1 MHz. The CLKS register bit allows the user to select the frequency
(1.048576 MHz or 1 MHz) used to automatically adjust symbol timing.
These bits determine the amount by which the frequency of the MCU CGMXCLK signal is divided to
form the MUX interface clock (f
They may be written only once after reset, after which they become read-only bits.
The nominal frequency of f
communications to take place. Hence, the value programmed into these bits is dependent on the
chosen MCU system clock frequency per
This bit determines whether the BDLC generates CPU interrupt requests in run mode. It does not clear
BSVR interrupts when exiting the BDLC stop or BDLC wait modes. Interrupt requests are maintained
until all of the interrupt request sources are cleared by performing the specified actions upon the
BDLC’s registers (or an MCU reset sets BSVR bits to $00). Interrupts that were pending at the time
that this bit is cleared may be lost.
If the programmer does not want to use the interrupt capability of the BDLC, the BDLC state vector
register (BSVR) can be polled periodically to determine BDLC states.
This bit determines the operation of the BDLC during CPU wait mode.
1 = Binary frequency, 1.048576 MHz
0 = Integer frequency, 1 MHz
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
0 = Run BDLC internal clocks during CPU wait mode.
1 = Stop BDLC internal clocks during CPU wait mode.
f
XCLK
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
Frequency
BDLC
BDLC
Table 15-2. BDLC Rate Selection
M68HC12B Family Data Sheet, Rev. 9.1
must always be 1.048576 MHz or 1.0 MHz for J1850 bus
) which defines the basic timing resolution of the MUX interface.
R1
0
0
1
1
0
0
1
1
Table
15-2.
R0
0
1
0
1
0
1
0
1
Division
1
2
4
8
1
2
4
8
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
f
BDLC
Freescale Semiconductor
BDLC
) must