M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 264

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

CLKSRC — msCAN12 Clock Source Flag
16.12.3 msCAN12 Bus Timing Register 0
SJW1 and SJW0 — Synchronization Jump Width Bits
BRP5–BRP0 — Baud Rate Prescaler Bits
264
msCAN12 Controller
This flag defines which clock source the msCAN12 module is driven from (only for system with CGM
module. See
The synchronization jump width defines the maximum number of time quanta (Tq) clock cycles by
which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the
bus (see
These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing,
according to
0 = msCAN12 clock source is EXTALi.
1 = msCAN12 clock source is twice the frequency of ECLK.
Table
Address: $0102
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is set.
The CBTR0 register can be written only if the SFTRES bit in CMCR0 is set.
Reset:
Table
Read:
Write:
16.9 Clock System
16-5).
BRP5
Figure 16-18. msCAN12 Bus Timing Register 0 (CBTR0)
16-6.
SJW1
0
0
0
0
1
SJW1
:
Bit 7
0
0
0
1
1
BRP4
Table 16-5. Synchronization Jump Width
0
0
0
0
1
:
SJW0
SJW0
6
0
Table 16-6. Baud Rate Prescaler
M68HC12B Family Data Sheet, Rev. 9.1
0
1
0
1
BRP3
and
0
0
0
0
1
:
BRP5
Figure
5
0
BRP2
0
0
0
0
1
:
16-7.
NOTE
NOTE
Synchronization Jump Width
BRP4
BRP1
4
0
0
0
1
1
1
:
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP0
BPR3
0
1
0
1
1
:
3
0
Prescaler Value (P)
BPR2
2
0
64
1
2
3
4
:
BPR1
1
0
Freescale Semiconductor
BPR0
Bit 0
0