M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 62

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

Central Processor Unit (CPU)
3.3.5 Program Counter
The program counter contains the address of the next instruction to be executed.
The program counter can also serve as an index register in all indexed addressing modes except
autoincrement and autodecrement.
3.3.6 Condition Code Register
S — Stop Disable Bit
X — XIRQ Interrupt Mask Bit
H — Half-Carry Flag
I — Interrupt Mask Bit
N — Negative Flag
Z — Zero Flag
V — Two’s Complement Overflow Flag
C — Carry/Borrow Flag
62
Reset:
Read:
Write:
Setting the S bit disables the STOP instruction.
Setting the X bit masks interrupt requests from the XIRQ pin.
The H flag is used only for BCD arithmetic operations. It is set when an ABA, ADD, or ADC instruction
produces a carry from bit 3 of accumulator A. The DAA instruction uses the H flag and the C flag to
adjust the result to the correct BCD format.
Setting the I bit disables maskable interrupt sources.
The N flag is set when the result of an operation is less than 0.
The Z flag is set when the result of an operation is all 0s.
The V flag is set when a two’s complement overflow occurs.
The C flag is set when an addition or subtraction operation produces a carry or borrow.
Bit 15
SP15
SP14
14
Reset:
Read:
Write:
SP13
13
U = Unaffected
Bit 7
S
1
SP12
12
Figure 3-9. Condition Code Register (CCR)
SP11
11
X
Figure 3-8. Program Counter (PC)
6
1
M68HC12B Family Data Sheet, Rev. 9.1
SP10
10
H
U
5
SP9
9
Unaffected by reset
SP8
8
4
1
I
SP7
7
N
U
3
SP6
6
SP5
U
2
Z
5
SP4
4
V
U
1
SP3
3
Freescale Semiconductor
Bit 0
C
U
SP2
2
SP1
1
Bit 0
SP0