M68HC12A4EVB Freescale Semiconductor, M68HC12A4EVB Datasheet - Page 239

• Manufacturer Part Number: M68HC12A4EVB
• Manufacturer: Freescale Semiconductor

Specifications of M68HC12A4EVB

• Lead Free Status / Rohs Status: Not Compliant

15.9.4 BDLC Data Register
This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC. It is
also used to pass data received from the J1850 bus to the CPU. Each data byte (after the first one) should
be written only after a Tx data register empty (TDRE) state is indicated in the BSVR.
Data read from this register is the last data byte received from the J1850 bus. This received data should
only be read after an Rx data register full (RDRF) interrupt has occurred. (See
Register.)
The BDR is double buffered via a transmit shadow register and a receive shadow register. After the byte
in the transmit shift register has been transmitted, the byte currently stored in the transmit shadow register
is loaded into the transmit shift register. Once the transmit shift register has shifted the first bit out, the
TDRE flag is set, and the shadow register is ready to accept the next data byte. The receive shadow
register works similarly. Once a complete byte has been received, the receive shift register stores the
newly received byte into the receive shadow register. The RDRF flag is set to indicate that a new byte of
data has been received. The programmer has one BDLC byte reception time to read the shadow register
and clear the RDRF flag before the shadow register is overwritten by the newly received byte.
To abort an in-progress transmission, the programmer should stop loading data into the BDR. This causes
a transmitter underrun error and the BDLC automatically disables the transmitter on the next non-byte
boundary. This means that the earliest a transmission can be halted is after at least one byte plus two
extra logic 1 bits have been transmitted. The receiver picks this up as an error and relays it in the state
vector register as an invalid symbol error.
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The service routines should clear all of the sources that are causing the pending interrupts. Clearing a
high priority interrupt may still leave a lower priority interrupt pending, in which case bits I0, I1, and I2
of the BSVR reflect the source of the remaining interrupt request.
If fewer states are used or if a different software approach is taken, the jump table can be made smaller
or omitted altogether.
Address: $00FB
The extra logic 1 bits are an enhancement to the J1850 protocol which
forces a byte boundary condition fault. This is helpful in preventing noise on
the J1850 bus from corrupting a message.
Reset:
Read:
Write:
Bit 7
BD7
Figure 15-16. BDLC Data Register (BDR)
BD6
M68HC12B Family Data Sheet, Rev. 9.1
6
BD5
5
NOTE
Indeterminate after reset
BD4
4
BD3
3
BD2
2
15.9.3 BDLC State Vector
BD1
1
Bit 0
BD0
BDLC Registers
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